The invention relates to timing apparatus for pulse code modulation, time division multiplex (PCM/TDM) switching networks having a number of word-organized storage locations equal to the number of PCM words per sampling pulse frame and an equal number of address memory locations individually assigned thereto for storing the addresses of the time slots during which the PCM information words retained temporarily in the word-organized storage locations shall be retransmitted.
Timing apparatus having the above characteristics has come into useage in the form of an associative storage (West German Offenlegungsschrift 2 158 683). Contrary to conventional digital data storages, there are no addresses serving exclusively for the identification of a memory location in an associative storage. Rather, the stored data themselves, or address data assigned to the useful data, (which may thus be considered as part of the stored data) assume the role usually performed by addresses. When searching for an item of information, an address word is simultaneously sent to all storage locations so that the searched item can immediately be found. Thus, the sequence in which the individual items are entered into such an associative storage is no longer of significance.
The use of such associative storages makes extensive decentralization of the PCM/TDM switching networks possible, since the use thereof enables the construction of modules allocated to the individual PCM trunks which are autonomous as far as their control is concerned (cf. West German Offenlegungsschrift 2 158 683).
The possibility of working with decentralized modules forming self-contained parts of the system offers great advantages when used with large-scale integrated circuits (LSI), because of the very small size of the components, the very low power dissipation, the great operational reliability of the components, and the small amount of inter-unit wiring between the components. Likewise, the use of a conventional associative timing circuit referenced above (West German Offenlegungsschrift 2 158 683) is suitable for implementation in large-scale integration, as far as its control autonomy is concerned. However, in order to operate such a timing circuit a serial-parallel conversion of the PCM words must be carried out prior to the actual time slot conversion.
The time needed for such conversion is particularly disturbing in conjunction with the integrated circuit design, because the operating speed of the components of such integrated circuits is from the outset lower than that of discrete components. Owing to the parallel representation of the PCM words, these circuit configurations necessitate many output leads. This, in addition to the single-use components that must be operated for the production means of such circuits, affects most frequently the cost factor.
Furthermore, the conventional timing apparatus does not admit of complementary operation, i.e., it is not possible to utilize one and the same memory location for both routes of data transmission.
An object of the invention is, therefore, to provide a timing apparatus that is particularly suited for implementation in large-scale integration, while obviating the problems referenced hereinabove.